Power optimization of real-time embedded systems on variable voltage processor

The growing class of portable systems, such as personal computing and communication devices, demands data- and computation-intensive functionalities with low power consumption. Such systems require design flexibility which result in the need for implementation on programmable processor platform. The main goal of this thesis is to present a methodology and a set of tools that support low-power core-based system design. This thesis introduces an approach based on a set of compilation and operating system-level techniques.; A collection of compilation techniques is developed to optimize throughput and the number of operations for general non-linear computations, the two most important components for low power consumption. Most of the previous results were restricted to limited classes of computations. This thesis addresses an optimal technique for throughput optimization of general non-linear computations using a set of transformations. An approach for automating the generation of the transformation script, given a set of transformations and applications, is also described. A novel divide-and-conquer compilation technique to minimize the number of operations for general non-linear computations is developed.; Recent advances in power supply technology along with custom and commercial CMOS chips that are capable of operating reliably over a range of supply voltages make it possible to create processor cores with supply voltage that can be varied at run time according to application timing constraints. The variable voltage processor core can be made to operate at different optimal speeds along its power vs. speed curve in order to achieve much higher energy efficiency than existing techniques for a wider class of applications than existing techniques. This adds another degree of freedom and complexity. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Several scheduling techniques for various design scenarios are described. This thesis also presents a design methodology which addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage processor core.