Methodologies for predictability optimization in VLSI systems

The main objective of this thesis is to provide an initial impetus towards a predictability driven design flow. It can basically be understood as the quantified form of accuracy of any pertinent cost function. Increase in predictability enables better design management and better interaction between high level and low level tools. This is highly instrumental in generating better quality designs. In this work, I focus on the resource binding problem to demonstrate the idea of predictability. First I focus on the low power problem and propose a spectrum of methodologies for improving power predictability in RT-Level designs. A comprehensive design flow is built which takes functions written in C and extracts data flow graphs. These DFGs are then scheduled and binded for power and predictability. Commercial tools like Synopsys design compiler and VSS simulator are used to characterize the modules for switching activity. This characterization is used by the resource binder to generate optimized solutions. The generated RT-Level designs are then translated into gate level using Synopsys design compiler. My experiments with Mediabench showed massive improvements in predictability with small increase in expected power dissipation. The multiple Choice Knapsack Problem (MCKP) has been studied and an ε-approximation algorithm is proposed. MCKP could be used to generate non-redundant solution w.r.t power and predictability. I also study methodologies for slack management in high level synthesis through resource binding. The extra slack in resources could be used to make the design robust to prediction inaccuracies and also to optimize the design quality. Large improvements in design quality are reported through effective utilization of this resource slack.