| The key rationale behind this thesis is the continued trend towards semiconductor device miniaturization. Bulk MOS has been the technology of choice since its inception. Though its dominance may wane in the near future, it is important to pinpoint its ultimate limitations. Therefore, this research focuses on the systematic investigation of the scaling opportunities and intrinsic performance characteristics of bulk MOS devices. The devices investigated include the uniformly doped surface channel inversion (UD-SCI) MOSFET, the retrograde doped surface channel inversion (RD-SCI) MOSFET, the buried channel accumulation (BCA) MOSFET and the surface channel accumulation (SCA) MOSFET. The Fermi-Threshold FET (FF) is examined as a special case of the SCA. Compact analytical drain current models with continuous and smooth transitions at regional boundaries are derived for each device. These models include carrier velocity saturation, mobility degradation caused by vertical and lateral high field effects, threshold voltage roll-off (ΔVT), subthreshold swing roll-up (ΔS), and velocity overshoot, all prominent characteristics of sub-micron devices. A key contribution of these models is the increased physical insight into the on/off current tradeoff that ensues with voltage scaling and is paramount to low voltage systems. Another vital contribution is the determination of general expressions for Δ VT and ΔS, applicable uniformly across all the devices under investigation. This allows a fair comparison of all devices, thus enabling the methodical description of the device characteristics required for gigascale/terascale (GSI/TSI) systems. |
