| Among all the issues that CMOS scaling has faced, increased power consumption in general and leakage power in particular are among the most important issues that the VLSI designers have to address. Due to the strong correlation between power consumption and operating temperature, increased power consumption compromises the reliability, functionality and performance of the circuits, either during chip normal operating condition or during test and reliability screening. Thermal modeling of high-performance circuits and systems is a crucial factor in order to achieve reliable and power-saving designs. The VLSI community currently lacks a way to model temperature at any level of design other than low-level circuits. The accuracy of thermal modeling has a substantial effect on the accuracy of thermal management studies of the processor architecture. Without this essential modeling capability, architecture researchers are limited to inaccurate estimation techniques, which will not be suitable for the thermal management of high performance circuits. In this thesis some of these issues are discussed and new models and associated CAD tools are developed. Various techniques at the circuit and system levels are explored.; In this thesis, a technique for junction temperature estimation is developed. Using this technique, the increase in the normalized junction temperature with scaling under nominal and burn-in conditions was predicted. This thesis also provide a new insight into the concept of thermal runaway and how it may best be avoided. Finally an electro-thermal tool was developed to study the low temperature operation of the high performance processors, while incorporating different techniques at circuit, and system levels. In this tool all the physical parameters of the chip at device, circuit and system level was incorporated and the tool was calibrated to an actual microprocessor. |
