Low complexity, high-speed VLSI architectures for error correction decoders

This thesis is devoted to the low complexity, high speed VLSI architectures for various error correction decoders.; To reduce the complexity of space-time block turbo coded system, a computationally efficient approach is proposed for the soft decoding of space-time block code, which can reduce the computation by up to 70 percent without any performance degradation. Additionally, for the considered outer code block turbo code, through reduction of test patterns scanned in the Chase algorithm and alternative extrinsic information computation, extra 0.3dB to 0.4dB coding gain is obtained with negligible hardware overhead. The overall complexity is approximately ten times less than that of the near-optimum decoder with coding gain loss of 0.5dB at the BER of 10-5 over AWGN channel.; Based on the proposed interleaved single parity check turbo product codes, a parallel decoding structure is developed to increase the throughput. A new interleaver is constructed to further improve the coding gain. The extremely simple sign-min decoding is derived with only two additions needed to compute each bit's extrinsic information. Important implementation issues such as the finite precision analysis, sorting circuit design and interleaver memory are also presented.; A systematic approach is proposed to develop high throughput decoder for quasi-cyclic low density parity check (LDPC) codes. Based on its properties, the two stages of belief propagation algorithm could be overlapped. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about two times assuming dual-port memory is available. Furthermore, a load balanced approach is presented to reduce the area of logic core. A FPGA/ASIC implementation of irregular LDPC decoder is also presented.; Long BCH codes achieve additional coding gain of 0.6dB compared to Reed-Solomon codes used for long-haul optical communication systems. A novel group matching scheme is proposed to further reduce the overall hardware complexity by 46% for BCH(2047, 1926, 23) code. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.