Super junction LDMOSTs for smart power ICs

This thesis deals with the design and implementation of Super Junction Lateral Double Diffused MOSFETs (SJ-LDMOSTs) targeting a wide range of smart PIC applications. The off-state performance of SJ-LDMOSTs implemented on finite resistivity substrates is affected by substrate-assisted-depletion effects. Original solutions to eliminate and/or suppress these effects are proposed in this thesis and lead to device structures which break the established Silicon Limit in terms of specific on-resistance (Ron.sp) and breakdown voltage (BV).; One proposed solution is the use of an insulating sapphire substrate, to eliminate charge coupling from the substrate and achieve charge compensation between the opposite polarity SJ pillars comprising the drift region. The uniform electric field distribution achieved in the SJ drift region and the high doping concentration in the SJ pillars result in a significant improvement in the Ron.sp for a given BV, particularly at high pillar height to width aspect ratio. To verify the viability of the structure, the design and implementation of SJ-LDMOSTs on silicon on sapphire (SOS) substrates using a custom 7 mask CMOS compatible process are described. The SJ pillars are generated using multiple high energy ion implantation to achieve well-defined vertical pillars. Experimental devices with drift region lengths of 66 mum and pillar width to height aspect ratio of 1.2 mum/0.7 mum exhibit R on.sp of 0.82 O.cm2 and BV ranging between 500 and 600V corresponding to less than 8.5% charge imbalance in the pillars.; In a second proposed solution, a 170V SJ-LDMOST implemented in a commercial 0.5 mum, CMOS/SOS process is presented to demonstrate that high voltage SJ-LDMOSTs can be fully integrated into a standard CMOS process. Fabricated devices featuring overlapping SJ pillars with drift regions of 10 mum and pillar aspect ratios of 0.3 mum/0.12 mum (effective width/height) exhibit Ron.sp of 87 mO.cm2 and BV of 170V.; A third solution to integrate SJ-LDMOSTs in mainstream CMOS technology using bulk silicon substrates is proposed. The device features a terminating RESURF region, inserted between the SJ drift region and the n+ drain to alleviate substrate-assisted-depletion effects. Simulation results on such devices predict that a significant reduction in Ron.sp for a given BV is achieved, as compared to conventional RESURF-LDMOSTs, using pillar height to width aspect ratios of 10 mum/1 mum.