| This thesis explores various high speed VLSI architecture design issues of parallel decision feedback decoders (PDFDs) and Tomlinson-Harashima precoders (TH precoders).; Based on an optimized scheduling scheme of the parallel decision-feedback decoding algorithm, a low complexity pipelined PDFD is proposed. A novel retiming and reformulation technique is proposed to further pipeline the low complexity PDFD with negligible hardware overhead. These two techniques are combined to develop three modified low complexity pipelined PDFD architectures.; Parallel PDFD architectures have been proposed based on the word-level parallelization technique for the Viterbi algorithm. Calculation results show that a 2-parallel PDFD can achieve a speedup factor of around 1.5.; By optimizing just at algorithmic and architectural levels, the speedup for the PDFDs may not be enough for some high speed applications. Thus, this thesis also considers system level optimizations for TCM (trellis coded modulation) systems with parallel decision-feedback decoding. Two interleaved TCM schemes are proposed for 10GBASE-T (10 Gigabit Ethernet over copper). Compared with the traditional scheme, these two TCM schemes can relax the inherent decoding speed requirements factors of 4 and 2, respectively. Due to intersymbol interference, the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than that in the conventional decoder. Thus this thesis also considers the problem of complexity reduction of the decoders for the two interleaved modulation schemes.; For the design of high-speed TH precoders, three approaches are considered. These include block processing, pipelining, and parallel processing. First, as TH precoders and decision-feedback equalizers (DFEs) have similar structures, the classical block processing technique for DFEs is extended to TH precoders. Second, novel pipelined architectures are proposed based on the view that a TH precoder is equivalent to an IIR (infinite impulse response) filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal. Third, a parallel TH precoder and its corresponding receiver structure are developed. Simulations show that the performance of the parallel TH-precoder is very close to that of the straightforward TH precoder. Their performance difference is within 0.1 dB. |
