| Superscalar processors are at the heart of many computing platforms – servers, desktop and laptop computers, and even cell phones. Moreover, superscalar processors have remained successful in general-purpose computing for many years because they exploit parallelism transparently. Several computer architecture trends suggest that now is the time to automate their development. These trends are (1) the growing interest in single-ISA heterogeneous multi-core processors, which are comprised of microarchitecturally diverse cores to attain higher performance and lower power consumption compared to a single generic core design, and (2) the demand for rapidly-designed, diverse, superscalar-based Application Processors (APs) in future mobile computing devices. A key barrier in the development of heterogeneous multi-core processors is the higher design and verification effort that comes with multiple core designs. Superscalar processor design automation helps in this respect, by raising the design abstraction to the level of diverse cores. The recent introduction of superscalar-based APs in smart phones and tablets is driven by increasingly complex software stacks (operating systems, virtual machines, just-in-time compilers, web browsers, and sophisticated “apps”). Superscalar processor design automation opens up APs to microarchitectural diversity within and across products, while maintaining rapid time-to-market.;This work proposes framing superscalar cores in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable. Moreover, FabScalar makes sophisticated cores more accessible to designers and researchers, fueling more innovation.;Fabricating a core requires reducing its RTL description to a layout, a step called physical design. Arguably, physical design is a significant portion of overall chip design cost. We present a detailed physical design study of FabScalar-generated cores. In keeping with FabScalar’s virtue of increasing accessibility through automation, we make a point of heavily relying on automated synthesis and place-and-route (SPR).;Finally, this work proposes a new heterogeneous multi-core design strategy: design-effort alloy, or DEA. In DEA, the processor is comprised of multiple core types: one is the flagship superscalar core or high-effort (HE) core and other types are low-effort (LE) cores. The HE core is mandatory for commercial viability of a high-end processor: maintaining leading-edge and robust performance that can only be reliably achieved with a highly optimized generic core. The LE cores target the HE core’s inherent compromises on outlier program phases, accelerating these outliers to further boost single-thread performance where possible. Much less effort is expended on microarchitecture tuning and physical design of the LE cores, however, to ensure that the overall enterprise is profitable. |
