| This thesis gives an overview of material and device research involving nanocrystalline silicon (nc-Si:H) for thin film transistors (TFTs) on organic polymer foil substrates. Among the several alternatives for semiconductor transistor back planes, nc-Si:H is pursued because of its potential advantages. These include a higher carrier mobility than hydrogenated amorphous silicon (a-Si:H), which makes nc-Si:H capable of complementary metal-oxide-semiconductor (CMOS) operation. nc-Si:H is compatible with organic polymer (plastic) substrates, is more uniform than polycrystalline Si made by excimer laser annealing, and, most importantly, it can be made with techniques and equipment that are compatible with the well-established technology for a-Si:H.; The nc-Si:H films were deposited by plasma enhanced chemical vapor deposition (PECVD) at substrate temperatures of 280°C to 150°C, which are considered ultra-low for conventional semiconductor technology. The structural properties, electrical properties and the chemical composition of nc-Si:H films were characterized by UV reflectance, scanning electron microscopy, atomic force microscopy, electrical conductivity, and secondary ion mass spectrometry. To raise the high field effect mobility and reduce the OFF current, the TFT channel layer of intrinsic nc-Si:H was deposited from source gases containing chlorine, at an excitation frequency of 80 MHz. While satisfactory properties were obtained for nc-Si:H, the deposition of the gate dielectric of ultra-low temperature remains an open challenge. Various dielectrics were investigated. Several pre- and post-deposition treatments were performed to improve their interface and bulk quality. Four different device geometries and associated fabrication steps were studied to maximize TFT performance while maintaining wide process windows. Both p-channel and n-channel nc-Si:H TFTs were made and integrated monolithically on glass and on Kapton E polyimide substrates. An electron field-effect mobility of ∼40 cm2V−1s −1 and a hole mobility of ∼0.35 cm2V −1s−1 were obtained, and inverters made by monolithically integrated p- and n-channel TFTs were demonstrated. But the high threshold voltages, gate leakage currents and drift observed in the TFT characteristics, and the large offset between the output voltage and the supplied HIGH voltage found in the inverter characteristics highlight the need for improving the gate dielectric and p+ contact. It is expected that after improvement of the gate dielectric and the p+ contact deposited at ultra-low temperature, directly deposited nc-Si:H circuits on plastic substrate will be available for flexible transistor back planes. |
