A CMOS tunable transmission line phase shifter and voltage-controlled oscillator for wireless communications

A fully integrated tunable transmission line phase shifter and voltage-controlled oscillator using a novel tank structure implemented using a transmission line and an accumulation NMOS varactor fabricated in CMOS are proposed in this thesis. As the required inductance at high gigahertz frequencies becomes smaller, only a single turn inductor is required. Since the single loop spiral inductor has various design issues due to negative mutual inductance, large area consumption, proximity effects from opposite terminals, etc., a transmission line, which has low loss and higher quality factor parties used instead. To transfer properties of the transmission line into circuit simulations without losing their uniqueness, an approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is developed. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electro-magnetic (EM) simulations for a small set of transmission line geometries spanning ranges of design parameter values. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.; To achieve a phase shifting function having lower transmission loss and better phase shift performance for transceivers in adaptive antenna array applications, a novel phase shifter requiring an ultra compact chip area using a 250nm CMOS process is developed. The proposed tunable transmission line phase shifter consists of a coplanar waveguide used as a lumped inductor merged with an accumulation NMOS capacitor for phase control.; An oscillator is implemented in a 250nm CMOS process using a differentially operated LC tank, which combines a transmission line inductor with an accumulation NMOS varactor to alleviate parasitic effects and increase phase noise performance. Unavoidable interconnect parasitics are absorbed into the LC tank component values at the beginning design stage.