Design and FPGA implementation of trellis coded modem based on DVB standard

This thesis concentrates on the implementation of a base-band modem specified by Digital Video Broadcasting (DVB) standard. The modem consists of Reed Solomon coding, Convolutional Interleaving, Pragmatic Trellis Coded Modulation (PTCM), and Pulse shaping filters. The system is employed in digital television and related applications based on satellite communications.; A design flow using System On a Programmable Chip (SOPC) is a novel approach that can be considered in the next generation of wireless modems. The design flow starts with modeling of the floating-point representation of the design in Simulink with parameters described in the DVB standard. Fixed-point refinement of the model is developed to compromise arithmetic precision for hardware simplicity. A number of significant simulations are performed to verify adequate precision of the fixed-point model by comparing the bit error rate curves with their floating-point counterparts.; Bottom-up design flow is used to synthesize the modem into the target hardware. The high-level abstraction model of the design is simulated and compiled into an FPGA using Xilinx System Generator for DSP. A novel clock distribution technique is proposed to achieve the highest possible clock frequency. Finally, the modem is synthesized and implemented in Xilinx Virtex II FPGA and post-place&route simulation is performed to ensure that the timing constraints are met. The implemented modem is able to transmit/receive digital audio and video signals up to 27.778 Mbit/s.