Novel Performance Enhancement Techniques for Delta Sigma Modulators for Telecom, Audio and Sensor Applications

The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design.;Combining both oversampling and quantization error shaping techniques, delta sigma (DeltaSigma) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS DeltaSigma ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for DeltaSigma ADCs in various application circumstances, such as telecom, audio, sensor, and so on.;First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 microm CMOS, measuring an image rejection ratio of 73 dB, being the best reported.;Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18-microm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB.;Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18-microm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors.