| One of the fastest growing trends in the semiconductor industry is the use of stacked dies. The desire to have smaller, lighter, and smarter devices drives the three-dimensional (3D) packaging technology.;However, the thermal issue is a big challenge in the stacked die packaging. Softie techniques such as the dynamic thermal management (DTM), the dynamic voltage scaling (DVS), and the thermal aware design are proposed to solve the thermal problem and to reduce the cooling and packaging costs. These methods require an accurate thermal model that is practical for architectural studies. HotSpot is an accurate and fast 2D thermal model suitable for use in architectural studies. It is based on an equivalent circuit of thermal resistances and capacitances that corresponds to micro architecture blocks and essential aspects of the thermal package [6 8 9].;Unfortunately, HotSpot is designed only for the 2D floor plan. In this project, I extend the 2D HotSpot model to a 3D thermal model for the stacked-die-package circuit design. The work includes modifying the software package to handle the thermal analysis of 3D stacked-die IC and applying the tool to demonstrate the effectiveness of a thermal aware design technique that is proposed by our research group. |
