Methodologies for Statistical Characterization of Circuit Reliability in Advanced Silicon Processes

Rising electric fields and imperfections due to atomic level scaling create non-ideal and stochastic electrodynamics inside a transistor. These appear as reliability mechanisms such as Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB) and Random Telegraph Noise (RTN) at transistor level, and as a convolved statistical manifestation in performance and functionality, at a circuit level. Compounded by shrinking operating margins with process variability and power constraints, these reliability issues have been propelled from device research arena to the forefront of chip design.;The first part of my thesis will explore these different reliability issues in three dedicated test chips. While device level probing has been de-facto estimation method for reliability engineers due to legacy and simplicity, the approach has become cumbersome due to time and effort needed to cover the required statistics. Conversely, we demonstrate circuit based reliability monitors which are a more scalable and representative alternative. The latter also enable superior timing resolution which is critical to record phenomenon such as BTI and RTN without measurement noise. For example, leveraging on-chip methods and intelligent timing control, we demonstrate a SRAMreliability macro with BTI estimation at three order smaller measurement times than possible using conventional approaches. On-chip logic could also be used to control test on large number of blocks resulting in a large experiment time speedup which is the basis for our TDDB macro.;The second part of my thesis will focus on 3D integration, a breakthrough technology for reducing interconnects delays and chip form factors. In particular, we measure the impact of chip stacking on power delivery and propose schemes to mitigate it through a statistical framework, fabricated in an actual 3D technology.;Overall, the ideas here can pave the way for not only accurate empirical modeling and robust guard-banding for pre-silicon phase but also post-silicon adaptive tuning. And thus we can better reap the benefits of these new silicon technologies.