High efficiency, low cost, fully integrated DC-DC converter solution

Rapid advances in the field of integrated circuit design has been advantageous from point of view of cost and miniaturization. However, power dissipation in highly integrated digital systems has become a major cause of concern. One of the methods to reduce power dissipation is to dynamically vary the supply voltage (DVS) of digital block depending on the load conditions. This requires high efficiency power converters to dynamically vary the supply voltage. Taking this a step further, the digital system can be further sub-divided into multiple independent voltage domains and DVS applied independently to these voltage domains. To economically support such an implementation fully integrated on-chip power converters are a way forward.;This thesis focuses on the design of fully integrated power converters to support DVS type applications. A switched inductive type converter is highly efficient as its efficiency depends only on the parasitics. But, a fully integrated switched inductive converter has some drawbacks and fails to support wide output power range. To circumvent the problem, we have implemented a switched inductive converter that operates in different modes based on the load that the converter supports. In these modes of operation, either the power switch size is scaled or the frequency is scaled to cut down the losses in the converter. The design achieves a peak efficiency of 74.5% and supplies a 450x output power range (0.6mW to 266mW).;A fully integrated capacitive converter with all digital ripple mitigation aimed at supporting the lower output power ranges has been designed. The capacitive converter uses a dual loop control, where a single bound hysteretic control loop achieves regulation and the secondary loop achieves ripple control by modulating capacitance size and charge/discharge time of the capacitance used to transfer charge from the input to output. The partial charge/discharge technique used to achieve ripple control does not degrade the efficiency, has been proved both theoretically and experimentally. The design taped out in IBM 130nm process achieves a maximum efficiency of 70% and reduces the measured ripple from 98mV to 30mV at 0.3V and 4mA load current.;A test-chip designed to study the impact of placing digital circuits underneath inductor used in power converter type applications is presented. The experimental results show the feasibility of implementing digital circuits underneath the inductor, thereby achieving higher area efficiency for the converter. Finally, a combined inductive/capacitive converter where the inductive converter supports the higher power range and capacitive converter supports the lower power ranges is described. The combined converter taped out in IBM 32nm SOI process achieves a maximum efficiency of 85.5% and a power density of 0.7W/mm2.;Additionally, we have also proposed a passive resonance reduction technique to reduce resonance on the supply line in bondwire based packages. The technique utilizes the area underneath the bondpad to implement passives required for resonance reduction.