| As Moore's law is followed closely over the past decades, down-scaling of transistor structure leads to a prominent improvement in its performance, in contrast, the development of interconnects is towards unfavorable direction. The reduction of wire width causes the resistive effect of interconnects to increasingly deteriorate signal delay and slew. As a result, in nanometer IC designs, the improvement of interconnect performance has gained significant importance. In interconnect-centric designs, the application of accurate delay models (including interconnect model and gate model) is one of the key issues. Some other concerns have become increasingly important, such as the reliability of signal nets and the effects of IR drop. In this dissertation, we investigate these issues and propose several approaches to handle these challenges.; Buffer insertion is an effective technique to improve the performance of interconnects. As modern IC designs get extraordinarily complex, design libraries may contain hundreds of different buffers and inverters. In buffer insertion techniques; to handle such a large library takes unaffordable runtime, particularly for those techniques, where high accurate delay models are applied. Therefore, in the first part of this dissertation, we propose several methods to cope with the large design library issue in buffer insertion technique. Buffers are not pruned from their libraries as in previous approaches, thus the solution quality is not sacrificed. Meanwhile, the runtime is reduced dramatically because, in our methods, the large number of time-consuming tree traversals becomes unnecessary for high order moment computations. Instead, moment values can be obtained from simple algebraic computations.; Although gate delay no longer dominate stage delay in the nanometer technology ICs, the gate modeling remains as a crucial issue in delay evaluations and its accuracy and efficiency have prominent effects on timing analysis and synthesis. Hence, in the second part of this dissertation, we present an explicit gate delay model, which is not sensitive to gate load and can be pre-computed before timing analysis and synthesis. Thus, the repetition of modeling work is totally unnecessary even when the gate load keeps on changing in performance optimization procedure. The efficiency is certainly improved in the synthesis/optimization loops. The advantage is attributed to using a second-order circuit. This two-pole approach also allows the model to yield an accurate result to match the nonlinear output of gate.; IR drop and ground bounce compromise the driving capability of gates and degrade IC performance, and even can make functional failure. Therefore, a timing model with consideration of IR drop/ground bounce is proposed in the third part of this dissertation. Comparing with traditional k-factor approach, this model does not require SPICE netlists and SPICE simulations. All the calculations in the proposed model are on the basis of the timing tables (delay table and transition table), which are available in the normal timing analysis. (Abstract shortened by UMI.)... |
