| Digital circuit testing is presented in this thesis. This thesis introduces an architecture that accelerates benchmarked circuit testing. Traditionally, benchmark circuits are tested on software, because of the complexity in developing a generic hardware architecture capable of testing sequentially or concurrently. The testing is based on Built-in Self-Test (BIST) techniques. The circuit testing is accomplished by two hardware implementations, aimed at increasing execution time with respect to its counterpart, software. The implementation realized and executed in hardware, illustrates the advantages of utilizing hardware platforms for digital circuit testing and it gives a path to developing more complex benchmarked circuits; which would have higher fault coverage.; The novel architecture is targeted for digital circuit testing and adaptive embedded system applications. These applications vary in their constraints (i.e. hard and soft real-time constraints) and environmental conditions (i.e. unknown and unpredictable).; The novel architecture consists of a fixed hardware unit and a Reconfigurable Processor Unit (RPU). The RPU employs hardware functional blocks. These Hardware Blocks (HB) encompass logic that targets their respective applications. We realize and implement HBs that target digital circuit testing applications, by means of BIST techniques.; Experimental results are presented in this thesis. In simple terms, the speedup factors are as high as 1 x 104 for sequential testing. |
