| This thesis presents the firmware design that drives hardware associated with the lowest level of data acquisition in the Radio Ice Cherenkov Experiment II (RICE II). The firmware is a FPGA design for a Virtex-4 LX that must buffer data from an 8-bit 2 gigasample/second ADC into a PC3200 DDR SDRAM module. Additionally, the design has logic in place that will upon request retrieve some of this data and foward it to an external USB2 controller chip without incurring any ADC buffering downtime. This thesis includes details on the synchronous design methods used, the verilog logic design, implementation results, and concludes with some recommendations for the future FPGA hardware and firmware optimizations. |
