| Multiprocessor computers are now common in the marketplace and will soon be on every desktop. A vital part of a multiprocessor computer's architecture is a definition of how the processors access common storage, that is, its memory consistency model. In order for programmers to write code that makes full use of the power of these computers they must comprehend completely the memory consistency model. The memory consistency model is usually complex, difficult to describe completely, and very difficult for programmers to use. The memory consistency models of the various architectures are often described using very diverse language. Attempts to simplify the language that describe the memory consistency models so that they are either easier for the programmer to use or so that similar descriptions can be used for various architectures generally fail to model all components of the system.;Using this framework two systems are defined; Itanium+A which is stronger than and Itanium+B which is weaker than the specifications of the memory consistency model from Intel's Itanium architecture. Itanium+A and Itanium+B differ very little. Itanium+A and Itanium+B are used to define the requirements for processor coordination on Itanium and to define and prove coordination algorithms for Itanium.;Outside of the framework, Sun's Sparc architecture and Intel's Itanium architecture are compared, using descriptions that follow each architecture's specification. This found similarities when resticted to very few memory access instructions, but general incomparability.;In this thesis a previous uniform framework for describing memory consistency models is extended, allowing a general description of the models of any architecture that completely captures the memory features. It can model the relationship between programs, written in whatever language the programmer chooses, and the computations that arise from executions of these programs on the chosen architecture. Also, it precisely models dependency relationships. |
