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FDTD methods using parallel computations and hardware optimization

Posted on:2008-07-29Degree:M.SType:Thesis
University:University of CincinnatiCandidate:Culley, RobertFull Text:PDF
GTID:2448390005455812Subject:Engineering
Abstract/Summary:
To achieve faster computation rates using cluster computers, reconfigurable resources are beginning to be utilized in computations. The Finite-Difference Time-Domain (FDTD) is a powerful method to solve differential equations that can be easily pipelined and placed into a Field Programmable Gate Array (FPGA) on a cluster. In this thesis, I show that the FPGA can be used to speed up a two dimensional simulation of a single precision FDTD computation on a cluster. One system demonstrated that the computation rate was two to four times faster when considered by itself; however, the means to transfers the data took more than 28 times the computation rate. A second system compared the full executable time of the program with hardware rates comparable to the software speed. Different methods of transferring the data were also tested. Overall, this shows that improvements can be made utilizing the reconfigurable resource to assist in the computation.
Keywords/Search Tags:Computation
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