Microarchitectures and synthesis compilers for efficiently executing imperative language programs

Superscalar processors no longer scale as silicon process sizes shrink. Spatial dataflow computing architectures have emerged as a promising and scalable alternative to superscalars, but this promise depends on deliver better performance and power efficiency than superscalars, and on software developers adopting spatial dataflow architectures.;My thesis research explores two spatial dataflow architectures, an application-specific architecture called CHiMPS and a tiled architecture called WaveScalar, which deliver on spatial dataflow's promise of performance and power efficiency, while simultaneously easing the programming burden by allowing developers to continue using their accustomed programming languages and execution model.;CHiMPS is a C-based synthesis compiler for heterogeneous CPU-FPGA computing platforms. CHiMPS facilitates FPGA programming by providing developers with performance that is greater and power consumption that is less than their current CPU platforms, but without sacrificing their familiar, C-based programming environment. The key to CHiMPS performance is its novel many-cache memory architecture. Many-cache creates multiple, multi-banked caches on top of an FGPA's small, independent memories, each targeting a particular data structure or region of memory in an application and each customized for the memory operations that access it. The caches are automatically generated from C source by the CHiMPS compiler.;WaveScalar took a different approach, starting with the same spatial dataflow computation model as CHiMPS, but using a tiled architecture, and aiming to replace the CPU entirely. I developed the WaveScalar microarchitecture, which involved designing, synthesizing, and evaluating four major RTL-level WaveScalar implementations to investigate different area, throughput, power, and clock-cycle trade-offs, and to prove the viability and low-complexity of the design. Each design supported the imperative language programming model, and matched or exceeded the performance and power efficiency of comparable superscalars.;My thesis research shows that spatial dataflow architectures are a powerful complement, if not replacement, for traditional superscalar processors, and their inherent scalability will continue to widen the gap between these two architectures. As a result, spatial dataflow looks even more promising as a way to return to the exponential growth in computing performance, and to the rapid pace of innovation in application domains that rely on an ever-increasing computing capability.