A programming model and processor architecture for heterogeneous multicore computers

Heterogeneous multicore computers, those systems that integrate specialized accelerators into and alongside multicore general-purpose processors (GPPs), provide the scalable performance needed by computationally demanding information processing (informatics) applications. However, these systems often feature instruction sets and functionality that significantly differ from GPPs and for which there is often little or no sophisticated compiler support. Consequently developing applications for these systems is difficult and developer productivity is low.;This thesis presents Merge, a general-purpose programming model for heterogeneous multicore systems. The Merge programming model enables the programmer to leverage different processor-specific or application domain-specific toolchains to create software modules specialized for different hardware configurations; and provides language mechanisms to enable the automatic mapping of processor-agnostic applications to these processor-specific modules. The Merge programming model has been prototyped on a heterogeneous system consisting of an Intel Core 2 Duo CPU and an Intel X3000 integrated GPU, and a homogeneous 32-way SMP system. Speedups of 3.6x-8.5x using the X3000 and 5.2x-22x using the 32-way system were achieved for a set of informatics applications relative to their single-core C reference implementations.;The Merge programming model facilitates heterogeneity throughout the system, including within the processor microarchitecture itself. This thesis presents novel chip-multiprocessor (CMP) with a modular microarchitecture that supports the integration of non-trivial specialized accelerators into GPP cores. The accelerators function as "add-ons", maintaining backward compatibility with existing designs, while offering features from GPUs and other more specialized systems. The extended CMP is evaluated using execution-driven simulation; speedups of up to 2.4x were achieved relative to the base CMP architecture.