A reconfigurable FFT architecture for OFDM based wireless standards

A mathematically efficient method to compute DFT and its inverse is done with the help of FFT algorithms. Several FFT algorithms implements DFT in an optimized way by reducing the number of redundant calculations. OFDM is one of the wireless communication standards that use FFT extensively. A large numbers of narrowband carriers present in the OFDM based standards are closely spaced in the frequency domain. A modern digital signal processing technique like FFT helps in avoiding a large number of modulators/demodulators and filters/complementary filters used at the transmitter/receiver respectively.In this work, a reconfigurable FFT processor is proposed applicable to various OFDM based wireless standards. The regularity in the butterfly structures is exploited to realize larger FFT points using 8-pt FFT. Although reconfigurable architectures do not lead to a low power design of processors, the overall versatility obtained by supporting various FFT lengths for different OFDM based standards is highly commendable. The proposed scheme reduces the complexity of the computation core in terms of hardware. Since the outputs of the butterflies from one stage is used as inputs to butterflies of next stage, buffering the intermediate results has reduced the number of memory writes and reads thereby reducing the power consumed. It is demonstrated that the proposed architecture achieves a more flexible (that supports many applications in OFDM based standards), and simpler design.