Nanostructure engineering using nanoimprint lithography and pulsed laser for nanophotonic devices

Faster, cheaper, and more portable electronic and optical devices require new fabrication technologies, device designs, and materials. Development of these sophisticated devices is enabled by nanoimprint lithography (NIL), a low cost, high throughput, high resolution, large area nanofabrication technology. Combining NIL with pulsed laser methods allows for the modification of materials at the nanoscale. This thesis presents work on the development of NIL and pulsed laser fabrication methods for nanophotonic devices and electronics on amorphous substrates.;In NIL, a mold deforms a layer of resist on a substrate, creating a surface relief pattern. We fabricated large area NIL molds with excellent uniformity by laser interference lithography. We also developed a novel method for the fabrication and duplication of NIL molds that avoids defects inherent in typical methods. Using conformal plasma deposition, we duplicated 200 nm period grating molds and 1 microm period grating molds bearing 50 nm features.;We fabricated and characterized a narrow-band tunable subwavelength resonant grating filter, fabricated by multiple-step NIL, which has applications in tunable lasers and optical networking. A 200 nm period grating, superimposed on a 1 microm period resonant grating, improved the alignment of a liquid crystal layer, increasing the filter tuning range from 2 nm to 21 nm.;We developed pulsed excimer laser processes to fabricate smooth silicon waveguides and crystallize amorphous silicon nanostructures. In a process called self perfection by liquefaction, a silicon strip waveguide was briefly melted by an excimer laser pulse, reducing the sidewall roughness from 13 nm to 3 nm. Low loss silicon waveguides are important for integrated nanophotonic circuits. We also used excimer laser pulses to crystallize amorphous silicon nanostructures fabricated by NIL. Using optical masks to create thermal gradients, we controlled the location and number of crystal grains during crystallization. This technique is applicable for fabrication of multilayer stacks of integrated circuits and thin-film-transistors on plastic substrates.