| This thesis proposes new amplifier architecture named Distortion Compensated Charge Transfer Amplifier (DCCTA) to reduce the non-linearity at the output of the conventional Differential Charge Transfer Amplifier (DCTA). The proposed DCCTA effectively reduces distortion in the amplified output signal by source degeneration, cross-coupling and making drain to source voltage of the amplifying transistor independent of the applied input signal resulting in an ENOB of 9.42bits, compared to 6.23bits for the DCTA at sampling frequency of 40MHz, while consuming only 13.5muW from a 1.2V source. Owing to the reduction in the non-linear distortion in the amplified output signal, a cyclic pipeline ADC is implemented using this DCCTA as a residue amplifier in the upper 10-bit resolution range, while maintaining' low power consumption in the overall ADC design. This cyclic ADC was simulated in 90nm CMOS process. The power dissipation for the whole design was 172.4muW from a 1.2V source producing an output digital code with an effective resolution of 9.21 bits. |
