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New techniques for addressing challenges of VLSI structural testing

Posted on:2007-06-20Degree:Ph.DType:Thesis
University:University of California, Santa BarbaraCandidate:Lin, Yung-ChiehFull Text:PDF
GTID:2446390005963781Subject:Engineering
Abstract/Summary:
As Design-For-Testability (DFT) techniques have become widely accepted and have achieved great improvements in product quality and reliability, these structural techniques have also introduced new test challenges. In this dissertation, we propose new methods to address such challenges, including over-testing, test data volume reduction, and multiple-fault diagnosis.; This dissertation consists of three parts. In the first part, we introduce the concept of pseudo-functional testing and two approaches to generate pseudo-functional tests. In the second part, we address the new requirements for compressing pseudo-functional tests. Moreover, a unified approach is proposed to enhance the efficiency of processes of test generation and test data volume reduction. In the third part, we present two methods, which can be applied individually and/or jointly, to improve multiple-fault diagnosis resolution and in turn to help the yield learning. This thesis sets forth the goal and contributions of our new techniques for addressing the challenges arising from the utilization of structural test generation methodology.
Keywords/Search Tags:Test, Techniques, Structural, New, Challenges
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