Integrating dual-Vth design flow using mixed Vth cell libraries in EDA tool

Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty.