Theory, implementations and applications of single-track designs

Asynchronous design is increasingly becoming an attractive alternative to synchronous design because of its potential for high performance, low power, and adaption to process variations and reduced EMI noise. However to compete with the existing synchronous designs there is a need to reduce the overwhelming design time of asynchronous designs by developing circuits that can easily be verified along with mature CAD flows to support them. In this thesis we propose to use template based methodology which facilitates standard cell based design that can easily be verified and allows using standard ASIC tools that have already been developed by semiconductor industry.;In this thesis we develop three novel non homogeneous single-track templates, including theory, CAD, and design examples. These static single-track templates follow a two phase static single-track handshake protocol and provide better performance than four phase asynchronous designs and better forward latency than asynchronous bundled data and synchronous designs. Compared with earlier homogeneous versions, non homogeneous single-track templates have the flexibility of having multiple levels of logic which helps in reducing the control area overhead by sharing the control logic among multiple levels of logic. These templates are more complex however and warrant more automation.;To quantify some of these advantages, an asynchronous turbo decoder was developed using a single-track standard cell library in IBM 0.18 mum technology and compared against a synchronous turbo decoder. Comparisons shows that asynchronous turbo decoder can provide 1.3X -- 2X improvement in throughput per area over the synchronous version for block sizes of 2K -- 768 bits. Moreover, due to its low latency advantages, it can support smaller block sizes at higher throughputs than possible using synchronous design.;To help automate such designs, we propose a CAD flow to synthesize single-track asynchronous design by extending an existing CAD tool called Proteus. Comparisons on ISCAS benchmarks shows that the proposed templates provide on an average 30% improvement in throughput per area over QDI templates and 75% improvement over MLD templates. We also demonstrate library characterization and SDF back annotation flow on a single-track standard cell library. Experimental results on a 64 bit prefix adder design indicates that the back annotation flow yields over two orders of magnitude advantage in simulation speed on analog verification flow with less than 5% error.;Finally we demonstrate the low latency and high performance advantages of single-track protocol over other asynchronous and synchronous communication protocols by comparing their throughput, latency, energy and bandwidth for a NoC interconnect link.