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Charge injection and clock feedthrough

Posted on:2011-01-18Degree:M.SType:Thesis
University:San Jose State UniversityCandidate:Yu, JonathanFull Text:PDF
GTID:2442390002457980Subject:Engineering
Abstract/Summary:
Turning off a transistor introduces an error voltage in switched-capacitor circuits. Circuits such as analog-to-digital converters (ADC), digital-to-analog converters (DAC), and CMOS image sensor pixels are limited in performance due to the effects known as charge injection and clock feedthrough. Charge injection occurs in a switched-capacitor circuit when the transistor turns off and disperses channel charge into the source and drain. The source, which is the sampling capacitor, experiences an error in the sampled voltage due to the incoming channel charge. Simultaneously, the coupling due to gatesource overlap capacitance also contributes to the total error voltage, which is known as clock feedthrough. In order to fully understand this behavior, charge injection and clock feedthrough are modeled, simulated, and measured. A basic charge injection/clock feedthrough model is first introduced to identify key components and explain fundamental behavior. This model is expanded upon by using Technology Computer Aided Design (TCAD) simulations, which can more accurately model the distribution of channel charge. TCAD simulations can also easily predict how charge injection and clock feedthrough are affected by various parameters, such as transistor operation, size, and geometry. Test structures are fabricated in a 0.18 mum CMOS process to measure and verify charge injection and clock feedthrough. It is shown that the model and simulations agree within 10%. The measurements are 40% higher than the model, but exhibit good trend agreement with the model and simulations.
Keywords/Search Tags:Charge injection, Model, Simulations
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