| As CMOS devices are scaled, the SiO2 layer becomes too thin to insulate. High-k materials allow scaling to continue, but there are band alignment problems. A high-k dielectric such as HfSiON, with a monolayer of La2O3 deposited on top, used in combination with TiN or TaN metal gates resolves this. This study examined the thermal stability of such stacks, as well as determining the actual structure of the gate stack. The samples were exposed to a 1000°C anneal for five seconds. This is a representative thermal treatment the devices experience during processing. The stack was analyzed predominately using AR-XPS. Backside SIMS determined if metals from the stack diffused into the bulk. Other methods such as XRD, RBS, MEIS, and AFM were used to confirm the findings. It was found that no detectable metal diffusion through the dielectric was observed, and the La 2O3 moved from the Hf-based dielectric to a SiON layer formed from the HfO2 deposition. |
