| Continued technology scaling has enabled the tremendous growth that semi-conductor industry has witnessed in the last half century. However, as the technology scales in into the deep submicron era, variability in device parameters and operating conditions is emerging as a major threat to this growth. In the face of increasing variability, traditional design approaches that use typical or worst-case values can lead to yield loss or increased cost and time to market, causing significant revenue loss in either case. State-of-the-art system-level analysis and design methodologies do not take the impact of variability into account and hence it is natural to question their effectiveness in the presence of variability. We believe that it is imperative that the impact of variability be considered during system level design. Analysis and design techniques that are cognizant of variability can help provide designers valuable feedback about the impact of variations early on in the design cycle and hence, facilitate better design decisions at the system-level while preventing expensive design re-spins.;The specific contributions on this thesis include: (i) system-level variability-aware power analysis methodology while considering the impact of manufacturing-induced variations in effective channel length and operation-induced variations in on-chip temperature, (ii) variation-aware system-level shutdown based power management techniques, (iii) variability-aware voltage level selection to improve the number of chips meeting power and performance targets, and (iv) a methodology for system-level performance analysis under variability, and various architecture level and application level techniques to enable performance recovery in systems affected by variations.;Experiments conducted on various Systems-on-chip designs demonstrate that variation-aware design techniques enable significant improvements in overall energy dissipation and performance characteristics. In particular, the resulting distributions are more favorable in terms of reducing the revenue loss due to variations. We believe that the approaches outlined in this thesis are useful with the existing design flow with the current technologies as well as in future systems by facilitating research and development in variation-aware application-level and architecture level techniques. |
