The Research And Realization Of The Internal Logic Test Method Of HDL Code

With the increasing application of FPGA in various important fields and the improvement of its complexity and importance,Hardware Description Language(HDL)has become a trend in circuit design.Therefore,the quality of HDL code has more and more significant impact on system security,which makes its reliability problem more and more prominent.Nowadays,how to ensure the quality of HDL code,which is one of the most important parts of the security of the design of FPGA,and how to quickly and efficiently find potential defects in the increasingly complex HDL code has become key research topics.Because the structure and development of the FPGA are similar to the software system,and the grammar and failure mechanism of the HDL are similar to that of the software language,the mature software testing theory and method can be used to test the internal logic of the HDL code.In this thesis,the relevant software testing theory and methods are studied,and according to the characteristics of the FPGA system and Verilog HDL,a testing method based on static structure analysis and weight calculation is proposed.By lexical analysis and conditional specification extraction of internal variables and program paths,this method obtains the relevant information within the code,and assigns weight to the extracted variables through the proposed subjective and objective weight analysis method.By calculating the weight coefficient,we can reasonably determine which program paths(intermediate variables)in the code are emphatically detected,which improves the efficiency of testing.At the same time,according to the extracted information and weight coefficients,it can guide the design of representative and targeted test case input data,and help to reduce the dimension of test case input data and locate code errors quickly.Finally,the test of the case code test demonstrates the feasibility and effectiveness of the test method for the combinational logic circuit.