Joint Detection And Decoding Receiver Of Polar Coded OFDM-IDMA Systems

Multiple access technique plays an indispensable role in modern wireless communication,which can improve the capacity of communication system by sharing the same resources for transmission.Since 5G wireless communication aims at higher spectrum efficiency,non-orthogonal multiple access(NOMA)has been proposed.The standard of NOMA is still under debate,so the research on NOMA draws a lot of attention from both academia and industry.Among many NOMA candidates,interleave division multiple access(IDMA)has been employed by the 4G LTE system to randomize interference,which makes IDMA a more practical technique with a sound theoretical basis.Nevertheless,there are still some issues to be addressed to meet the requirements of the 5G communication system.Although IDMA can increase the spectrum efficiency due to supporting overload transmission,it brings high multi-user interference at the same time.So the IDMA system demonstrates disappointing bit error rate(BER)performance in low signal to noise ratio(SNR)region.In this paper,polar codes are applied to the conventional OFDM-IDMA system for further performance improvement due to its capacity-achieving capability.Based on the proposed polar-coded OFDM-IDMA system,detection and decoding schemes are further explored,containing separated detection and decoding(SDD)scheme and joint detection and decoding(JDD)scheme.Later,taking(128,64)polar codes as an example,the simulation platform is constructed for performance comparison of different detection and decoding schemes.Under the same computational complexity,the proposed JDD scheme has obvious performance gain over the SDD one,with 0.7 d B performance gain when BER is 10-4and 1.2 d B performance gain when FER is 10-2.In order to further improve the detection efficiency of JDD,early termination strategy is introduced in this paper,containing LLRs aided JDD(LA-JDD)and signs aided JDD(SA-JDD).Based on these early termination criteria,simulation verification is carried out.According to numerical results,the computational complexity can be reduced to 43.9% of that in the original JDD almost without performance degradation when SNR is 6 d B.So early termination strategies can remove redundant iterations of JDD,which enhances the adaptability of this system.To further evaluate the practicality of the receiver,this paper presents the architecture design of the JDD receiver.Meanwhile,approximation strategy is adopted for hardware-friendly implementation.In addition,the JDD receiver is synthesized in a 28 nm CMOS technology whose ASIC results have demonstrated that the approximation strategy indeed contributes to the area-cost reduction.Compared with related works,the implementation of the JDD receiver is reasonable.