Research And FPGA Implementation Of BD Navigation Adaptive Anti-jamming Algorithm

Satellite navigation has many advantages such as all-weather,high accuracy,and continuity,so it is widely used in military and civilian fields.However,as the electromagnetic environment becomes increasingly complex,the vulnerability of satellite navigation signals makes it extremely vulnerable to intentional or unintentional interference.Therefore,research on satellite navigation anti-jamming technology has an important role in improving the stability of satellite navigation.This article starts with the analysis of the array structure and signal processing.First,it introduces the widely used principles of airspace filtering and space-time two-dimensional filtering.Then it describes the common criteria for adaptive beamforming,and studies the applicable environment and filtering effect of different criteria.Based on the characteristics of the navigation satellite signals,the power inversion algorithm based on the linearly constrained minimum variance criterion is suitable for anti-jamming processing.The anti-jamming performance of the algorithm is specifically studied.The weight solution is the core of the navigation anti-jamming hardware implementation.This paper then studies several common weight solution methods such as matrix inversion algorithm(SMI),least mean square algorithm(LMS)and recursive least squares algorithm(RLS),and points out the direction for the realization of weight solution in hardware.Aiming at the problem that the computational complexity of hardware implementation increases sharply when the number of array antenna elements is large,this paper studies the array dimension reduction technology,and discusses the design of the dimension reduction filter and the anti-interference performance changes before and after the dimension reduction.Secondly,this paper studies the design of digital hardware system and software system based on FPGA.The designed hardware core circuit includes the design of ADC circuit,high precision clock circuit and DAC circuit.The system has studied software design,including the design of driver,FIFO data synchronization,band-pass filter,Hilbert transform,RLS algorithm module and dimensionality reduction algorithm module.The data structure of state machine plus pipeline in the iterative calculation module is proposed to increase the calculation speed of the RLS iterative module by 71%.Finally,the simulation and experimental test of the hardware implementation are designed.The hardware experiment includes the soft construction of the test platform,the four-element circular array space-time anti-jamming external field experiment and the four-element uniform linear array airspace dimensionality reduction algorithm experiment.The space-time anti-jamming test results show that the Beidou navigation anti-jamming processing board designed in this paper has a good anti-jamming effect;the dimensionality reduction experiment shows that the dimensionality reduction algorithm used in this paper can significantly reduce the calculation amount of the algorithm,and at the same time improve the SJNR.