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Research On The Acceleration And Optimization Method Of Convolutional Neural Network

Posted on:2020-01-05Degree:MasterType:Thesis
Country:ChinaCandidate:J J WangFull Text:PDF
GTID:2428330620956148Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
As the most widely used model in the field of image classification and recognition,Convolutional Neural Networks have shown excellent performance in the fields of image recognition,image classification and natural language processing.With the increase of model parameters and network size,the deployment of CNNs on resource-limited platforms is limited by the consumption of time and large occupation of resources.In this paper,the model compression and model acceleration of convolutional neural network are studied from the aspects of software and hardware,and experiments are designed for verification.The specific work is as follows:Firstly,this paper takes the classic handwritten character recognition network LeNet-5 as an example to introduce the basic structure of convolutional neural network and analyze the calculation process of each network layer.According to the analysis of the basic structure and the training process,this paper comes up with the CNNs model's optimization methods respectively from the fitting of the control,the choice of the activation function,weights initialization method,the pretreatment of the training data and the optimization of network parameters.In terms of software,this paper designs two schemes of compression and acceleration,and combines network optimization methods to improve model performance.The first scheme is to improve the traditional weight pruning,starting from cutting the parameters and neurons of the fully connected layer,and combining the idea of the fusion branch to achieve further acceleration of the model.The improved weight pruning transforms the dense network structure into a sparse structure,and the parameter size is reduced while the model size is compressed and accelerated.In addition,the idea of probabilistic pruning used in this paper reduces the proportion of false pruning compared to traditional decisive pruning.The second scheme is based on the idea of Deep Separable Convolution.Starting from improving the structure of the convolutional layer,the standard convolution operation is separated into depthwise convolution and pointwise convolution.At the same time,the idea of fusion branch is combined to realize further acceleration.The scheme achieves the effect of model compression and acceleration by reducing the parameters of the convolutional layer and reducing the computational quantities.The size of model compression depends on the size of the improved convolutional layer.Experiments show that the more convolutional layers are separated,the more obvious the compression and acceleration effect will be on the model.In addition,this paper studied the network optimization scheme for the improved model of scheme 1 and scheme 2 through experiments,and realized the improvement of accuracy by adjusting network parameters to compensate the precision loss caused by model compression and model acceleration.In terms of hardware,FPGA was selected as the hardware acceleration platform of Convolutional Neural Networks.The parallelism of Convolutional Neural Networks is highly explored through a large number of programmable logic resources of FPGA,and the acceleration of LeNet-5 model in forward prediction process is realized.In addition,HLS is adopted for fast FPGA design and development,and optimization methods such as pipeline optimization,storage optimization and cyclic expansion optimization are combined to further accelerate the prediction process.The experiment was verified based on the MNIST handwritten digital data set.The experimental results showed that compared with the software,the hardware acceleration platform achieved the same accuracy while achieving three times of speed improvement.
Keywords/Search Tags:Convolutional Neural Networks, network optimization, model compression, branch fusion, FPGA acceleration
PDF Full Text Request
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