The Optimization And Verification Of Snooping Boadcast Potocol Component Of Domestic Processor

The birth of multi-core multi-processor technology makes the processor perform more tasks in a shorter period of time,greatly improving the performance of the processor.Cache consistency is the key technology to achieve multi-core multi-processor.Cache consistency technology determines the correctness and performance of the processor,and has been widely concerned by enterprises and research institutes at home and abroad.Cache consistency is the key technology to achieve multi-core multi-processor.Cache Coherence Association—The MESIF protocol was first proposed by Intel Research.The consistency protocol divides the implementation method into source monitoring and directory monitoring according to different issuers of monitoring requests on the hardware.According to the different write-back main storage strategies,it can be divided into write-through and write-back.According to the way of writing data to update the cache of other processors,the protocol can be divided into write update and write invalid.This article analyzes and compares the above methods.This paper analyzes the implementation of the MESIF protocol by a domestic server processor and verifies the consistency processing module(CPM)in the processor.The author used SystemVerilog language to build a four-processor direct connection model of the source monitoring protocol,tested various scenarios of CPM,found design bottlenecks,proposed optimization solutions,and optimized chip performance.The simulation results show that the fair rotation design method improves the fairness of the processor in handling conflicting transactions;Increasing the engine pipeline effectively improves the transaction throughput rate;By expanding the capacity of the received data buffer,the occurrence of protocol deadlock is avoided.The specific work and optimization points of this article are as follows:(1)Analyzed the mainstream implementation of MESIF protocol,analyzed and compared the differences and applicable scenarios of source monitoring and directory monitoring,the advantages and disadvantages of write update and write invalid,write penetration and write-back strategies Advantages and disadvantages.(2)The implementation of the MESIF protocol by a domestic server processor is studied,and a simulation verification environment is built around the consistency processing module CPM in the processor.The implementation scenario of the consistency protocol under the direct connection of four processors is simulated.(3)The verification requirements of CPM are proposed,and the implementation sequence of the consistency process in CPM is described using PSL language.Build different scenes to verify the focus of CPM,and use function coverage and code coverage as indicators to achieve double coverage.(4)By modifying the verification environment,constructing special scenarios to perform performance tests on CPM,querying design bottlenecks,proposing optimization schemes,and optimizing chip performance.Through the differentiation engine method,the throughput of consistent transactions is improved;by changing the processing mechanism of the same address transaction,the fairness of different processors to the same address transaction processing is optimized;the error scenarios in the design are reproduced,and by adding anti-death The lock mechanism ensures the correctness of the design.The research methods used in this paper have a good reference and application value for the realization of multi-channel direct-connect distributed storage access architecture processors in the future.