| In recent years,Data Center Network(DCN)has become a critical infrastructure worldwide.It is expected that by 2021,94% of the work and computational tasks in the world will be processed through data center and the total traffic of cloud data center will reach 19.5ZB every year.Given that DCN is playing an increasingly prominent role in Internet and network latency is a key factor that affects the development of cloud computing services in data center,it is crucial to reduce latency in DCN.Technical studies on low latency in DCN hold untold promise for possible applications in improving network service and user experience.Many researchers have proposed their low latency schemes for DCN,including:(1)the scheme that improves transport protocol based on TCP congestion control(e.g.DCTCP and D2TCP);(2)the scheme that optimizes traffic through flow scheduling(e.g.PDQ and PIAS);and(3)the control scheme based on SDN(e.g.OpenTCP and TCCS).The Next Generation Internet Research Lab of Tsinghua University proposed the Active Buffer Queue(ABQ)scheme of DCN.According to the ABQ scheme,the pace of backward acknowledgement packet in network flow is adjusted by deploying active buffer queue on the switch.In this way,a fine-grained rate adjustment can be realized to alleviate network congestion and reduce network latency.Most studies use network simulator as a means of test,evaluation and verification of low latency schemes of DCN,but software simulation has such disadvantages as low fidelity and low efficiency.NetFPGA is an open source platform that Stanford University developed for network-related experiment.As a line-rate(Gb/s)hardware development tool,it enables researchers to test the hardware feasibility and performance of new network models in a near-real environment.Based on an in-depth study of NetFPGA SUME(the new state-of-the-art platform of NetFPGA),the ABQ scheme was implemented and its hardware feasibility and performance reliability were verified.The paper mainly consists of the following parts:(1)The research status of low latency schemes of DCN and the NetFPGA platform was investigated.Based on an in-depth study of NetFPGA SUME,its hardware architecture,development environment setup,development process,data path and standard interface were summarized in details to facilitate subsequent research.(2)The ABQ scheme was partly optimized and improved according to the characteristics of NetFPGA SUME.In the implementation of the ABQ scheme,the queuing discipline of the scheme was also redesigned according to the characteristics of the platform.Specifically,the original linear programming was replaced with an approximate fine-grained multi-intervalfragmentation threshold method.The redesigned queuing discipline can be easily implemented on NetFPGA SUME,and also improves the rate of resource utilization.(3)The ABQ scheme was realized on the basis of NetFPGA SUME.The scheme's hardware feasibility was verified by providing a reliable high-performance test environment.Its performance was also validated by comparing with the DCTCP scheme based on NetFPGA SUME.(4)The ABQ scheme and the DCTCP scheme were simulated and verified by using the simulator in Vivado.The performance of the ABQ scheme in both the ALL-to-ALL and Incast scenarios was tested by designing the test plan for ABQ and building the simulation environment for DCN.Experimental results suggest that the ABQ scheme has relatively low and stable latency,higher performance and a more promising future,as evidenced by a 22.5% decrease in average latency compared with the DCTCP scheme. |
