Efficient Implementations Of Evolutionary Algorithms On RISC-V Architecture

In many areas of academic research and industrial production,evolutionary algorithms are used to optimize and solve real-value problems.As population-based stochastic optimization methods,compared to traditional gradient methods,evolutionary algorithms lack gradient information and optimization direction,requiring a large number of iterations to optimize and solve the problem,and there is a deficiency in operational efficiency,which is an important factor constraining the application of evolutionary algorithms.In order to address this challenge,this topic revolves around evolutionary algorithm operational efficiency and hardware acceleration from the perspective of computer architecture.Based on the state-of-the-art reduced instruction set computing V(RISC-V)architecture,this topic investigates the operational efficiency of three single-objective evolutionary algorithms,particle swarm optimization(PSO),differential evolution(DE)and covariance matrix adaptation evolution strategy(CMAES),and two multiobjective evolutionary algorithms,non-dominated sorting genetic algorithm II(NSGA-II)and stochastic ranking-based multi-indicator algorithm(SRA).The CEC'05(presented at the 2005 IEEE Congress on Evolutionary Computation)and DTLZ(initials of the four authors)benchmark functions with different parameters are used as the problems,hardware emulation is used as the validation method,and the number of cycles consumed by evolutionary algorithms is used as evaluation indicator of the operational efficiency.The aim is to study and design efficient implementations of evolutionary algorithms on RISC-V architecture.In the first part of this topic,a preliminary study of the operational efficiency of evolutionary algorithms is investigated around the memory system of the RISC-V architecture.It was found that there is a risk of performance degradation of the cache when evolutionary algorithms are running,which affects the operational efficiency of evolutionary algorithms.To address this risk,we design a RISC-V architecture that runs evolutionary algorithms relatively efficiently at the level of the memory system,as a basis for further research.It was also found that there may be time-consuming operations in multi-objective evolutionary algorithms that severely affect the operational efficiency,which has more room for improvement compared to singleobjective evolutionary algorithms and will be the focus of further research.The second part of this topic revolves around the operational efficiency of two multi-objective evolutionary algorithms,NSGA-II and SRA.We design two coprocessors to accelerate non-dominated sorting,the time-consuming operation of NSGA-II,and calculation of indicators,the time-consuming operation of SRA respectively,and the two co-processors are validated on DTLZ benchmark functions with different scales.The validation results show that that these co-processors achieve 7?11X acceleration for non-dominated sorting and 1.4-2X acceleration for NSGA-II algorithm,and 18?34X acceleration for calculation of indicators and 11-26 X acceleration for SRA algorithm.The two co-processors improve the overall operational efficiency of the NSGA-II and SRA algorithms and achieves the efficient implementations of the corresponding evolutionary algorithms on RISC-V architecture.