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Microprocessor-oriented Data Encryption Storage And Transmission Method

Posted on:2019-07-10Degree:MasterType:Thesis
Country:ChinaCandidate:S ZhaoFull Text:PDF
GTID:2428330611993166Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of mobile Internet and handheld and wearable smart devices,embedded microprocessors have entered people's daily lives.However,it should not be overlooked that the embedded microprocessor is likely to be maliciously attacked in the process of information interaction,which brings security risks.This paper is based on the open source RISC-V instruction set architecture microprocessor.By introducing the Physical Unclonable Function component to generate the encryption/decryption key,a security module can be designed for the confidential storage and transmission of information on the microprocessor,which avoids the transmission of user unencrypted data on the bus.At the same time,the algorithm improves the attack difficulty of multiple chip attacks:A framework structure for secure microprocessor data encryption/decryption transmission mechanism is proposed.Firstly,the AES core algorithm is improved,and the address feedback mode is introduced to complete the encryption/decryption in a single cycle,shortening the first data response time of the microprocessor,and satisfying the requirement of the microprocessor to quickly throughput data by using a ten-stage pipeline structure,reduces the signal-to-noise ratio during data processing,and provides system-level encryption support for user data.Secondly,a weak PUF structure is designed to realize the secret generation of algorithm keys in the security module.The PUF structure can effectively prevent physical attacks.Combined with the security module,the security level of the microprocessor is greatly improved.A set of security specifications including microprocessor security work scenarios,data storage and bus transmission is proposed,and different processing mechanisms are given for data of different dense levels.Based on the structural framework of the secure microprocessor data transmission mechanism,combined with the working mechanism of the RISC-V instruction set architecture microprocessor,the cipher module with safe strength configurability,low overhead and high efficiency is realized.Based on the XILINX ZYNQ7000 development board,the PUF design and function verification are realized.The core module of the security module is implemented by Verilog hardware description language.The circuit function simulation verification is completed by using Modelsim.Experiments show that the security module design implements the expected working mechanism and can quickly encrypt/decrypt sensitive information in the memory.
Keywords/Search Tags:Microprocessor Security, Physical Unclonable Function, RISC-V instruction set architecture, AES
PDF Full Text Request
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