Research And Design Of Brain-like Computing Accelerator Based On FPGA

Deep learning has demonstrated excellent performance in many fields such as speech recognition,object detection,natural language processing,and autonomous driving.But behind the high accuracy,there are many limitations such as high computational cost and weak general intelligence.The neuromorphic computing based on Spiking Neuron Networks(SNN)is considered to be a better way to solve the problem of artificial intelligence due to the working mechanism closer to the biological brain,which is expected to overcome the deficiencies of deep learning.However,how to meet the needs of high performance,low power consumption,and adapt to scale expansion is still a challenging problem that neuromorphic computing systems need to solve.Because there are many types of neurons and synapses,and SNN is still in the research stage,out of flexibility and difficulty of implementation,at this stage,software is used to simulate and study SNN.The SNN software simulator NEST has many support neurons and synaptic models,and it is more focused on the scale,dynamics and structure of SNN,and is favored by brain scientists and computational neuroscientists.However,due to the architecture of the CPU itself,the NEST emulator runs slowly on the CPU platform and has high power consumption.In response to these problems,the main work and innovations of this article have the following aspects:First,in order to analyze the reason for the slow simulation speed of the NEST simulator,a quantitative experiment for the NEST simulator is designed.Analyze the working principle and calculation-intensive points of NEST pulse neural network simulator,quantify the experimental data,and analyze the simulation time of each part.Two typical cases are used to verify the computationally intensive points of the proposed NEST simulator,and to provide theoretical and experimental support for later hardware acceleration.Secondly,according to the characteristics of the NEST simulator's large amount of synapse calculation,the FPGA acceleration of the Spike Timing Dependent Plasticity(STDP)type synapse is designed.Due to the limited FPGA resources,the design of the hardware circuit uses a local parallel + pipeline architecture to increase the data throughput and calculation parallelism.For complex calculation formulas,optimize the calculation structure while ensuring correctness,so as to reduce the use of on-chip resources.The acceleration scheme adopts the heterogeneous scheme of ARM+FPGA,the processing system(Processing System,PS)end is responsible for the operation of the top-level framework of the NEST simulator,and the programmable logic(Programmable Logic,PL)end is responsible for synaptic computing acceleration.Experimental results show that the single-node performance of the synaptic accelerator designed in this paper is 61.79 times that of ARM-A9 and 4.1 times that of Xeon E5-2620.In terms of energy efficiency ratio,it is 115 times that of Xeon E5-2620 and 55.5 times that of ARM A9.Thirdly,FPGA acceleration of IF neurons is designed in response to the characteristic of large calculation amount of neurons in NEST simulator.The FPGA acceleration scheme designed uses a pipeline + parallel structure.Similar to the designed synaptic hardware accelerator,on the ZYNQ-based hardware and software platform,the FPGA part is responsible for the calculation of the neuron part,and the ARM part is responsible for the operation and communication of the system.In terms of performance,single-node performance is 1.9 times that of Xeon E5-2620.