Visual Design Method Of Very Large Scale SoC Based On IP Cores

Visual design method of very large scale SoC based on IP cores is proposed in this paper,including visual IP cores management,visual IP cores invocation,visual IP cores configuration and visual modules connection.The specification of IP core encapsulation is formed at the same time.This design method can simplify the development work and increase the design efficiency.Specific EDA software tool is designed to support this visual design method of SoC.The research work including software architecture,abstract modeling and graphic user interface.This software utilizes the MVC architecture that separates Mode and View following the principle of weak coupling,which can make the software project coherent,clear and easy to modify and extend.In Mode layer,IP model with versatility and scalability is established to describe the run-time IP cores data.Wire node mode and wire net mode is established based on the circuit analysis theory,which is used to describe the connection between I/O ports of modules.In View layer,module widget and wire widget is designed based on QT graphics view framework.On one hand,the widgets present the information of Mode layer.On the other hand,the widgets help to control the logic of Mode.Following the design principles for interface programming,polymorphic object oriented programming thought is used in this section.Complex data structure is designed to describe the topological structure of wires in the design work of wire widget.The Controller layer updates the data in Mode layer to View layer and submits the configuring and connecting operations from View layer to Mode layer after analysis.At the same time,it is used to check the validity of the operations in View layer.Invalid and illegal operations will be filtered out while the operation signal is transmitted.Aiming at the engineering demand,MI interface IP core is designed for this EDA tool.This module is used to convert the CPU protocol and AXI protocol.FIFO bypass structure is proposed to reduce the delay time during burst write require.Four stage pipeline is design for the read require to give full play to the advantages of AXI protocol.