Research And Implementation Of Automatic White Balance Algorithm For SOC

In recent years,with the popularity of smart phones,cameras and other devices as well as the coming of artificial intelligence era,people have put forward higher and higher requirements for image quality.Image signal processor is the core of the whole imaging system and determines the final image quality.Automatic white balance is an important part of the whole image signal processor,which is used to correct the whole image color deviation caused by the color temperature of the light source,so that the image can restore the color of the object itself better and improve the image quality.Based on the study of various automatic white balance algorithms,an improved automatic white balance algorithm based on color temperature curve is proposed from the point of view of ensuring the effect of automatic white balance and suitable for hardware implementation.This algorithm combines the gray world algorithm and the white balance algorithm of color temperature curve,analyzes the distribution of different color system points B/G and R/G under different color temperature conditions,filters the gray system points in the image according to the distribution' conditions,and takes the information of the filtered points as the relevant data of white balance processing.In the process of white balance processing,the image anti-jitter function is added to solve the problem of image over-processing which may occur due to instantaneous mutation in the environment.By adopting the adaptive variable step size progressive adjustment strategy,the flicker problem of the display screen affected by the real-time environment is solved,and the actual user experience is improved.The algorithm avoids the failure of monochrome scenes,improves the implementation effect of automatic white balance algorithm,and reduces the complexity of algorithm,hardware implementation complexity and hardware resource overhead while ensuring the calculation accuracy.After the algorithm verification effect meets the design requirements,combined with the overall SOC architecture design,Verilog HDL is used for sub-module design.In the submodule design,the pipeline design is adopted to improve the processing speed.At the same time,in view of the large amount of data to be processed,an algorithm compression strategy is proposed,which can effectively reduce the data processing capacity,reduce power consumption,reduce resource overhead and improve processing speed on the premise of having little impact on accuracy.For some modules,time-sharing reuse is designed to reduce resource overhead and power consumption.After the submodule design is completed,the system integration and logic synthesis are completed.The comprehensive results show that the module can meet the design requirements.Compared with before optimization,the area is reduced by 29.2%and the power consumption by 32.6%.Finally,FPGA prototype verification shows that the module has a good effect of automatic white balance.