Research On The Fast Synchronization Estimation Algorithm And Circuit Design For The High-speed Ad Hoc Network Nodes

The Ad Hoc network is different from the cellular mobile communication system,it does not rely on the central base station and it can directly establish a self-organized networks between terminals of both sides for communication,which can meet the communication requirements between wireless portable devices.The Ad Hoc network can play an important role in some special fields(such as disaster rescue,battlefield communication,etc.).Improving the data transmission speed of Ad Hoc network is one of the main research contents of high-speed Ad Hoc network.OFDM technology is the preferred implementation technology of high-speed Ad Hoc network,and the synchronization module is a key component in OFDM systems.The performance of the synchronization module directly determines the communication performance of the system.Compared with cellular mobile communication systems,Ad Hoc network nodes have the characteristics of low power consumption,weak data processing capacity,complex working environment and large randomness of the relative position change of communication nodes.Therefore,efficient and fast synchronization is very important to improve the quality of high speed Ad Hoc network communication.This thesis mainly studies the synchronization problem in high-speed Ad hoc network.For the synchronization estimation algorithm,we mainly study the non-data-assisted algorithms,including the maximum likelihood estimation algorithm,the minimum mean square error estimation algorithm and the maximum correlation estimation algorithm,which are based on cyclic prefix.This thesis compares the advantages and disadvantages between different algorithms in high-speed Ad Hoc network synchronization applications,and according to the requirements of high-speed Ad Hoc network,the minimum mean square error estimation algorithm in non-data-assisted algorithms is simplified to reduce the computation of the estimate.In order to achieve the purpose of fast synchronization,this thesis also proposes a new OFDM data frame structure,which makes the synchronization speed faster and reduces the amount of computation.Through the simulation verification platform based on MATLAB/Simulink software,the fast synchronization method proposed in this thesis is simulated,The simulation results show that compared with the traditional OFDM synchronization estimation method,the communication quality of the proposed method does not decrease obviously under low SNR channel conditions,but the synchronization speed is greatly improved.In this thesis,the hardware design of synchronization module is completed,and the joint simulation of software and hardware is carried out.Simulation results show that when the data frame length is 160 samples,the proposed synchronization estimation is 112 sample periods faster than traditional OFDM synchronization estimation,and it uses fewer FPGA resources and reduces the total power consumption by 0.026 W.On the premise of not reducing the communication quality,less hardware resources and lower power consumption are applied,and higher synchronization speed is obtained,which meet the requirements of high-speed Ad Hoc network for fast synchronization and portable hardware energy saving.