Research And FPGA Implementation Of Pedestrian Recognition Based On Deep Learning

Pedestrian re-identification refers to pedestrian matching in a multi-camera network with non-overlapping fields of view.It can identify a given pedestrian target from pedestrian images captured by multiple cameras.Pedestrian re-identification has extremely high application value in intelligent video surveillance and has important research significance.This paper proposes a deep learning-based pedestrian re-identification algorithm,which is used in laboratories,classrooms and other places that need to have a certain real-time recognition of matching pedestrian targets.The algorithm is implemented on FPGA(Field Programmable Gate Array)verification.The main research contents and conclusions of this article are as follows:This article first introduces basic theories related to pedestrian re-recognition.After analyzing the advantages and disadvantages of various types of pedestrian re-recognition algorithms,we finally choose a deep learning-based method to solve pedestrian re-recognition tasks;then,we introduce the basic principles of convolutional neural networks in deep learning And detailed analysis of the Improved DL network based on deep learning algorithms.In order to make the Improved DL network model structure fulfill the real-time requirements in the application scenarios of this paper,an improved deep learning-based pedestrian re-recognition algorithm is proposed to improve the performance of the scenario for the pedestrian re-recognition algorithm.One-time pedestrian re-identification speed,reducing the amount of network calculations.In the experiment of this paper,the Market1501 database training test results show that the pedestrian re-recognition speed is better than the Improved DL network.Implement and verify the hardware on the basis of completing the algorithm design.Because FPGA has certain advantages in terms of computing speed and power consumption,FPGA hardware implementation is used to increase hardware resources and accelerate its calculation process.The hardware design framework of this article mainly includes a network computing module,an SD card(Secure Digital Memory Card)control module,an SDRAM(synchronous dynamic random-access memory)control module,and a top-level control module,in which the network computing module is responsible for running network data calculations;The SD card control module is responsible for storing pedestrian image data and network parameters.The SDRAM control module is responsible for caching network parameters and data in the network operation module.The top-level control module ensures the correct reading of pedestrian image data and the correct calculation of the network operation module data.The cache data can be written and read out in time to coordinate the operation of each module.This paper uses Verilog language to describe the overall hardware design of register conversion level,and to perform functional simulation of each hardware module to verify its logic function.Finally,the overall hardware program is compiled and downloaded to the FPGA development board,which verifies the correctness and feasibility of the algorithm hardware implementation.