Design And Application Of Coarse-grained Reconfigurable Neuromorphic Array

In recent years,big data and artificial intelligence have flourished.The best deep learning technology is used to extract,classify and recurs data,and it has a wide range of applications in computer vision,natural language processing and intelligent system decision making.The realization of learning algorithms in hardware has become a hotspot in computer hardware research.However,with the gradual improvement of network scale and complexity,traditional computer hardware obviously cannot meet the required acceleration performance,so how to accelerate the calculation of neural network is the key issues to be solved.In just a few years,all kinds of artificial intelligence chips have sprung up,but the performance of the chips is mixed,most are just simple arithmetic stacks and can only speed up specific network layers.and rarely applicable to the neural network structure of rapid iteration.Therefore,the design of the neural network hardware structure with superior performance and reconfigurable configuration is particularly important.This paper mainly designs a Coarse-grained Reconfigurable Neuromorphic Array(CRNA)that can be used for neural network acceleration.For the limited computing resources(small storage space,limited power consumption,short response time,etc.),a new neural network accelerator structure suitable for mobile terminal sensing processing is designed,which broadens the hardware application field based on neural network.In this paper,all-digital circuits are used to design coarse particles digital neurons,which include fixed-point multiplication and addition,convolution mapping,and activation.And integrated 128 neurons as a neural network operator,the neurons are highly unified in structure,and there is no cross-access,which perfectly realizes the cascade expansion of the neuron array,and can realize any number of integrations.The input and output layers of the neural network use serial shift registers to realize the inflow and outflow of data,which avoids the problem of storage bandwidth encountered when array parallel computing accesses storage,which is different from the traditional von Neumann centralized instructions/data.The structure of reading and writing,the hidden layer realizes the parallel computing of neurons through the design of distributed storage(parameter localization),and the coordinated scheduling of data flow and parameter flow solves the communication bottleneck of data and instruction in neural network calculation,avoiding the memory Frequent access,reduce the power consumption of storage and reading,and achieve ideal parallel computing.The neuron array uses a reusable deployment method to calculate the network layer slice partition by sliding window.The neural network layer of any number of nodes can be deployed,and the output layer of the upper layer is used as the input of the current layer,and the multi-layer nerves are deployed in sequence.The network realizes multiple mapping modes of neurons through its flexible configuration and reconstruction,and realizes the complete mapping of the neural network from algorithm to hardware.According to different network model structures,different network parameters and weights are configured to accelerate the multi-layer hybrid neural network.Compared with the general neural network accelerator,the coarse-grained reconfigurable neuromorphic array designed in this paper has superior weight,efficient data,parameter access mechanism and extremely high utilization efficiency of computing nodes.Due to the evolution and application of intelligent terminals,the neural network under the neural network accelerator is also larger and larger,and the required storage resources are larger.This design specifically implements the expansion of DDR3 on FPGA for large-scale neural networks.To store huge neural network weights.Support for large-scale neural network acceleration has been achieved.