Hardware Implementation Of Small Target Detection And Encoding Algorithm For Infrared Image

Infrared image detection has many advantages such as long distance,strong penetration and all-weather work.It has been widely used in precision guided weapons.Infrared image target detection is a key component of precision guided weapon detection,and it will affect the accuracy of weapon strikes.In addition,infrared image compression coding is a necessary way to solve the problem that the bandwidth of infrared image transmission is narrow.Therefore,the research of efficient infrared small target detection and coding algorithm and its hardware implementation has important scientific significance and application value.In order to meet the application requirement that precision guided weapons can detect and encode infrared images in real time,a hardware circuit of infrared image target detection based on attribute filter and guided filter is designed and implemented by high level synthesis circuit design method,and a hardware circuit of region of interest coding based on shift of background bit plane for infrared image sequence is designed and implemented.And the hardware system of real-time infrared image target detection and coding is realized on the XC7K325 T FPGA hardware platform.The main research work of this paper can be summarized as follows:Firstly,aiming at the problem of low processing speed in the hardware implementation of attribute filtering algorithm,a parallel processing method based on one-dimension window for maximum or minimum value in row and column direction is proposed by analyzing the principle and speed bottleneck of the algorithm,and a fully pipelined circuit is designed and implemented.The experimental results show that the attribute filter can achieve the processing speed of 3195 fps with resolution of 256*256,and process 191 frames more per second,compared with the hardware architecture proposed by Debasish Mukherjee et al.Secondly,aiming at the problems of low data throughput and large storage resource cost in hardware implementation of guided filtering algorithm,a parallel processing method of row and column summation for data reuse and fully pipelined circuit is proposed by analyzing data processing flow of the algorithm and allocating the processing order of the related operations.The experimental results show that the guided filter can achieve the processing speed of 208 fps with resolution of 720 p,which is 2.02 times faster than the hardware architecture proposed by Charan et al.Lastly,in order to alleviate the transmission pressure of narrow bandwidth channel,a region of interest coding hardware system for infrared image sequence based on background bit plane shift is designed and implemented.The region of interest can be coded first to retain more information of target region by reducing the numerical value of the background region.The experimental results show that the average PSNR is 45 d B after 32 times compression of the infrared test image,and the processing speed can reach 352 fps with resolution of 256*256.