Single Image Haze Removal Using Color Attenuation Prior And Its Implementation On FPGA

Fog and haze appear frequently in China and have a wide distribution area,which not only affects the visual presentation of outdoor scenes,but also causes degradation of outdoor shot images,resulting in partial or large loss of image information directly.Therefore,it is necessary to find a more effective image dehazing technology to reduce or eliminate the influence of hazy in the original hazy image and improve the quality of the hazy image.In this paper,based on the color attenuation a priori image dehazing algorithm,an improved color attenuation prior dehazing algorithm is proposed and implemented on FPGA.The main research contents and conclusions of this paper are as follows:Firstly,the reason of image degradation is analyzed,and then the atmospheric physical model is introduced to restore the degraded image information;Secondly,combining with the advantages and disadvantages of the dark channel prior image dehazing algorithm and the color attenuation prior image dehazing algorithm,an improved algorithm is proposed,which improves the model of scene depth;Finally,subjective and objective comparisons between the restored image of the algorithm and restored i:mages by other algorithms are presented.The experimental results show that the proposed algorithm has superiority to image dehazing.Implementation and verification of the algorithm by applying FPGA.The hardware design mainly contains the calculation of transmittance and the estimation of atmospheric light value A.In the module of calculating the transmittance value,the depth of scene is obtained by using the improved depth model and corresponding floating-point calculation,and then the transmittance is obtained by invoking the exponential IP core.In the estimation of the atmospheric light value A module,the maximum value in the dark channel data can be quickly compared by the design of the maximum value comparison module,and map the corresponding position of the maximum value in the three channels of R,G and B of the original image,and get the corresponding pixel value at the position,and then through the operation of the maximum comparison module,the final top value is A.The system are compiled and synthesized in the Quartus ? environment,and the DE2-115 development board is used for board level verification.The results show that the output of the system board level verification on FPGA is consistent with the simulation result in Modelsim,and the running speed of the algorithm on the FPGA is increased to the millisecond level,which indicates the correctness of the hardware design and meets the real-time requirements.