Design And Optimization Of Dual-GCT Press-package Structure

In order to better adapt to the needs of power electronics applications,power semiconductor devices are gradually moving toward high voltage,high current,high frequency,fast and miniaturization,so they must withstand higher power density and higher junction temperature,which leads to temperature of device rise,thus affecting device performance and reliability.As the operating frequency continues to increase and the size shrinks,the switching losses and electromagnetic interference of the device become more and more serious.In addition to considering the heat dissipation characteristics,parasitic inductance has become a focus of current research.According to the structural characteristics of Dual-GCT,a press-pack packaging of Dual-GCT is designed,the thermal characteristics of the package structure are analyzed and the parasitic inductance of the package structure is extracted.The main research contents are as follows:Firstly,The package structure of the crimped GCT is analyzed.According to the structural characteristics of the Dual-GCT and its installation requirements with the driver board,a press-pack packaging structure matching the Dual-GCT chip is designed,including the double gate component and the tube and other accessories.Secondly,Analysis the thermal characteristics of the Dual-GCT press-pack structure.The temperature distribution and thermal stress distribution of the package structure under a given power consumption are analyzed by ANSYS software.The results show that the temperature distribution and thermal stress distribution of the package structure are close to symmetry,and the maximum temperature is 102.2 ℃ and is located at the chip;The thermal stress distribution simulation of the package structure under thermal shock and high and low temperature cycling conditions shows that the maximum thermal stress of the package structure is located at the outermost periphery of the package,and has no effect on its thermal reliability.Lastly,In order to extract the parasitic inductance of the sector-cathode in the dual-core GCT package structure,the package structure model was established in Maxwell software,andthe electromagnetic density distribution was simulated to obtain the parasitic inductance of thestructure.The results show that the parasitic inductance of the gate-to yin in the dual-core GCTpackage structure is 4.36 nH,which provides a basis for the design of the gate drive circuit of the dual-core GCT.