The Design Of High Dynamic Performance Control Algorithm For 100W Primary Side Regulation Flyback Converter

For its simple structure and low cost,Primary-Side-Regulation(PSR)flyback converter is widely used in the fields of power supply for consumer electronics.And digital control technology is becoming the research hotspot because of its flexibility.Due to the indirect sample method of output voltage for primary-side-regulation structure and the time-consuming mode switch process of traditional multi-mode control method,the dynamic performance of the digital controlled PSR flyback converter is not ideal.Aiming at the problems mentioned above,a high dynamic performance control algorithm for 100 W PSR flyback converter with synchronous rectification structure is proposed in this thesis.Firstly,the basic theory of high dynamic performance control algorithm is introduced from three aspects: digital multi-mode control method,charge-discharge control in dynamic process,load detection.Secondly,the concrete solutions are proposed,including:(1)Two dynamic modes are introduced on the basis of traditional multi-mode,to improve the flow of mode-switching in dynamic response process;(2)Aiming at light-to-heavy load transient,a constant current charge method in CCM is utilized to increase the energy input into secondary-side,which can pull up the output voltage quickly;(3)Aiming at heavy-to-light load transient,a quick discharge method based on synchronous rectification structure is utilized,so that the energy is steered away from the output capacitor to the primary-side,which can pull down the output voltage quickly;(4)A load detection method based on the voltage slope is utilized to calculate the load value of the system.Then according to the load value,the system would jump to an appropriate steady mode to remove the voltage fluctuation when dynamic modes are disabled.Thirdly,the behavioral modeling of the high dynamic performance control algorithm is implemented,and the RTL-Level simulation of the proposed algorithm is implemented by Simulink and Modelsim.Finally,the effectiveness of this proposed algorithm is verified by FPGA in a power supply system of 20V/5A.According to the test results,without affecting the other performance of the system,in the load range 100% ~ 0.5% transient,the maximum overshoot voltage and undershoot voltage are reduced from 3.15 V to 1.732 V and from 5.02 V to 1.879 V,respectively.The maximum undershoot and overshoot recovery time are reduced from 83.43 ms to 1.787 ms and from 40.32 ms to 1.888 ms,respectively.And the peak efficiency of the system is up to 95.26%.The test results meet the requirements of the design specifications.