Research And Implementation Of Time Domain Acquisition Technology For 10GHz Broadband Signal

The real-time sampling rate of acquisition system can be effectively improved based on high-speed ADC(analog-to-digital converter)time alternating sampling technology,but the system bandwidth is still limited by the analog bandwidth of single ADC.Due to the insufficiency of input bandwidth of current high-speed ADC,the range of signal frequency that can be obtained is limited,which becomes a bottleneck of high-speed signal acquisition in time domain.Based on the "T/H(track/holder)+ADC+FPGA" architecture,this paper uses equivalent sampling technology to design a broadband acquisition system,which can effectively improve the input bandwidth of high-speed acquisition system.The main research tasks include the following aspects:1.The research of T/H and its circuit design: the working principle and main parameters of T/H are studied,and the mathematical model of T/H circuit is built.How T/H affects the system performance and how to fundamentally improve the input bandwidth of ADC is studied and analyzed.The "T/H+ADC" acquisition architecture is built,which converts the high-speed changing signal into the slow-changing signal and sends it to the low-bandwidth ADC for sampling,thus effectively improving the input bandwidth of the acquisition system.2.Clock scheme design of broadband acquisition system: According to different sampling methods,different clock generation schemes are designed.A sampling clock with low jitter and 5 ps unit step delay is designed to achieve sequential equivalent sampling.A real-time sampling clock generation circuit for broadband acquisition system is designed based on dual-loop PLL(phase-locked loop).The sampling clock with high precision and high stability is realized by configuring PLL and designing loop filter circuit parameters.3.Design of data acquisition,reception and storage: Demonstrating different acquisition schemes based on ADC,studying the evaluation method of ADC,evaluating and selecting ADC,configuring,adjusting and correcting ADC according to demand.The FPGA is used to receive the 4-channel 12-bit single-line 500 Mbps high-speed data stream collected and quantized by ADC,and the DDR data is converted into SDR through IDDR and then cached them into 8-way synchronous FIFO.4.Design of data processing part: Communication with FPGA based on STM32 by means of FSMC(flexible static memory controller),realizes the control of ADC,PLL and delay unit,reads the data in FIFO,and merges the multi-channel data to the upper computer for display.5.Research on trigger circuit design and delay nonlinearity: analysis of trigger principle,design of trigger signal generating circuit of acquisition system;research on the influence of delay nonlinearity of delay chip on acquisition system,and use standard signal comparison method to correct delay module.Based on sequential equivalent sampling technology,the system finally achieves the equivalent sampling rate of 200GSa/s,and successfully acquires and reconstructs 10 GHz broadband signal.